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chào mọi người, mình không rõ định nghĩa về BCD Adder và BCD Couter có gì khác nhau sau khi đọc bài này( do trình độ anh ngữ còn kém)
"A binary coded decimal (BCD) adder. Note that you should only apply input values from 0..9 to the inputs of the adder, because the remaining values A..F are undefined for BCD arithmetic. Click the hex-switches or use the 'a' and 'b' bindkeys to select the input values for the adder.
Naturally, it would be easy to design a special circuit for the binary coded decimal arithmetic. However, this is seldom done.
The circuit shown here relies on the same trick that is often used in microprocessors for BCD arithmetic instructions. For example, many microprocessors including the Intel 808x and Motorola 68xx families provide a special decimal adjust accumulator instruction (DAA). A BCD addition is then performed in two steps, namely a standard addition followed by the DAA instruction. The basic operation performed by DAA is to add a constant value of 6 for each bcd-digit that overflowed during the first addition. Only very little logic is required to implement this operation.
To make this behaviour explicit, the circuit shown in the applet uses two stages of binary adders, each built with a single 7483 4-bit adder. The first stage consists of just the binary adder. The second stage uses a few gates to check for a decimal overflow, that is, output values larger than 9. If an overflow is detected, the second adder is hardwired to add the value 6 (0110) to the output of the first adder - which is equivalent to a subtraction of 10, thereby undoing the overflow of the first stage. The resulting 4-bit output value and 1-bit carry are the correct sum in BCD arithmetic.
Circuit Description
A 4-bit BCD-counter built with JK-flipflops. This is an asynchronous implementation of a cascadable, 4-bit, binary-coded decimal counter. In total, the circuits needs just the four flipflops and one additional AND gate.
Click the clock switch or type the 'c' bindkey to operate the counter. (To keep the schematics as readable as possible, separate power-on-reset components are used for each flipflop in the example. No bindkeys are used for the power-on-reset components.)
The basic structure is just the asynchronous counter, with the Q output of one counter stage used as the CLK input for the next stage. Due to the AND-gate in front of its J input, the Z3 flipflop is only set when both Z1 and Z2 are 1 and Z0 generates a 0-1 edge. These conditions are only met when counting from seven to eight, correctly setting the Z3 flipflop. At the next clock input to Z3, while counting from nine to ten, the J input of Z3 is zero and the flipflop is reset to 0. At the same time, flipflop Z1 is also reset the NQ output of flipflop Z3 is still zero, inhibiting the transition of Z1 to 1, so that the counter correctly counts from nine to zero."
các bạn biết j cụ thể hơn thì giải thích giúp mình với. cám ơn các bạn nhiều
"A binary coded decimal (BCD) adder. Note that you should only apply input values from 0..9 to the inputs of the adder, because the remaining values A..F are undefined for BCD arithmetic. Click the hex-switches or use the 'a' and 'b' bindkeys to select the input values for the adder.
Naturally, it would be easy to design a special circuit for the binary coded decimal arithmetic. However, this is seldom done.
The circuit shown here relies on the same trick that is often used in microprocessors for BCD arithmetic instructions. For example, many microprocessors including the Intel 808x and Motorola 68xx families provide a special decimal adjust accumulator instruction (DAA). A BCD addition is then performed in two steps, namely a standard addition followed by the DAA instruction. The basic operation performed by DAA is to add a constant value of 6 for each bcd-digit that overflowed during the first addition. Only very little logic is required to implement this operation.
To make this behaviour explicit, the circuit shown in the applet uses two stages of binary adders, each built with a single 7483 4-bit adder. The first stage consists of just the binary adder. The second stage uses a few gates to check for a decimal overflow, that is, output values larger than 9. If an overflow is detected, the second adder is hardwired to add the value 6 (0110) to the output of the first adder - which is equivalent to a subtraction of 10, thereby undoing the overflow of the first stage. The resulting 4-bit output value and 1-bit carry are the correct sum in BCD arithmetic.
Circuit Description
A 4-bit BCD-counter built with JK-flipflops. This is an asynchronous implementation of a cascadable, 4-bit, binary-coded decimal counter. In total, the circuits needs just the four flipflops and one additional AND gate.
Click the clock switch or type the 'c' bindkey to operate the counter. (To keep the schematics as readable as possible, separate power-on-reset components are used for each flipflop in the example. No bindkeys are used for the power-on-reset components.)
The basic structure is just the asynchronous counter, with the Q output of one counter stage used as the CLK input for the next stage. Due to the AND-gate in front of its J input, the Z3 flipflop is only set when both Z1 and Z2 are 1 and Z0 generates a 0-1 edge. These conditions are only met when counting from seven to eight, correctly setting the Z3 flipflop. At the next clock input to Z3, while counting from nine to ten, the J input of Z3 is zero and the flipflop is reset to 0. At the same time, flipflop Z1 is also reset the NQ output of flipflop Z3 is still zero, inhibiting the transition of Z1 to 1, so that the counter correctly counts from nine to zero."
các bạn biết j cụ thể hơn thì giải thích giúp mình với. cám ơn các bạn nhiều
