Ai Biết về VHDL làm ơn giúp em với, đang cần gấp, huhu!

[kenji76]

thấy em cho bài VHDL bảo về biên dịch và giải thích từng ví dụ rồi nộp, nhưng em ko hiểu gì hết, mong các anh chị làm ơn giúp đỡ ( nếu được làm ơn biên dịch và giải thích từng ví dụ dùm em, em cám ơn nhiều lắm):


Ví dụ 1:

PROCESS(x)
SUBTYPE smallreal IS REAL RANGE -1.0E6 TO 1.0E6;
VARIABLE q : real;
BEGIN
q := smallreal’LEFT;
-- use of ’left returns
-- -1.0E6
END test;


Ví dụ 2:


PROCESS(a)
TYPE bit_range IS ARRAY(31 DOWNTO 0) OF BIT;
VARIABLE left_range, right_range, uprange, lowrange :
integer;
BEGIN
left_range := bit_range’LEFT;
-- returns 31
right_range := bit_range’RIGHT;
-- returns 0
uprange := bit_range’HIGH;
-- returns 31
lowrange := bit_range’LOW;
-- returns 0
END PROCESS;


Ví dụ 3:


ARCHITECTURE b OF a IS
TYPE color IS (blue, cyan, green, yellow, red, magenta);
SUBTYPE reverse_color IS color RANGE red DOWNTO green;
SIGNAL color1, color2, color3,
color4, color5, color6,
color7, color8 : color;
BEGIN
color1 <= color’LEFT; -- returns blue
color2 <= color’RIGHT; -- returns magenta
color3 <= color’HIGH; -- returns magenta
color4 <= color’LOW; -- returns blue
color5 <= reverse_color’LEFT;
-- returns red
color6 <= reverse_color’RIGHT;
-- returns green
color7 <= reverse_color’HIGH;
-- returns red
color8 <= reverse_color’LOW;
-- returns green
END b;


Ví dụ 4:

PROCESS(a)
TYPE bit4 IS ARRAY(0 TO 3) of BIT;
TYPE bit_strange IS ARRAY(10 TO 20) OF BIT;
VARIABLE len1, len2 : INTEGER;
BEGIN
len1 := bit4’LENGTH; -- returns 4
len2 := bit_strange’LENGTH; -- returns 11
END PROCESS;

Ví dụ 5:

PACKAGE p_4val IS
TYPE t_4val IS (’x’, ’0’, ’1’, ’z’);
TYPE t_4valX1 IS ARRAY(t_4val’LOW TO t_4val’HIGH) OF
t_4val;
TYPE t_4valX2 IS ARRAY(t_4val’LOW TO t_4val’HIGH) OF
t_4valX1;
TYPE t_4valmd IS ARRAY(t_4val’LOW TO t_4val’HIGH,
t_4val’LOW TO t_4val’HIGH) OF t_4val;

CONSTANT andsd : t_4valX2 :=
((’x’, -- xx
’0’, -- x0
’x’, -- x1 (Notice this is an
’x’), -- xz array of arrays.)
(’0’, -- 0x
’0’, -- 00
’0’, -- 01
’0’), -- 0z
(’x’, -- 1x
’0’, -- 10
’1’, -- 11
’x’), -- 1z
(’x’, -- zx
’0’, -- z0
’x’, -- z1
’x’)); -- zz
CONSTANT andmd : t_4valmd :=
((’x’, -- xx
’0’, -- x0
’x’, -- x1
’x’), -- xz (Notice this example
(’0’, -- 0x is a multidimensional
’0’, -- 00 array.)
’0’, -- 01
’0’), -- 0z
(’x’, -- 1x
’0’, -- 10
’1’, -- 11
’x’), -- 1z
(’x’, -- zx
’0’, -- z0
’x’, -- z1
’x’)); -- zz
END p_4val;

Ví dụ 6:

PROCESS(a)
VARIABLE len1, len2, len3, len4 : INTEGER;
BEGIN
len1 := t_4valX1’LENGTH; -- returns 4
len2 := t_4valX2’LENGTH; -- returns 4
len3 := t_4valmd’LENGTH(1); -- returns 4
len4 := t_4valmd’LENGTH(2); -- returns 4
END PROCESS;

Ví dụ 7:


LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
ENTITY shifter IS
PORT( clk, left : IN std_logic;
right : OUT std_logic);
END shifter;
ARCHITECTURE structural OF shifter IS
COMPONENT dff
PORT( d, clk : IN std_logic;
q : OUT std_logic);
END COMPONENT;
SIGNAL i1, i2, i3: std_logic;
BEGIN
u1: dff PORT MAP(d => left, clk => clk, q => i1);
u2: dff PORT MAP(d => i1, clk => clk, q => i2);
u3: dff PORT MAP(d => i2, clk => clk, q => i3);
u4: dff PORT MAP(d => i3, clk => clk, q => right);
checktime: PROCESS(clk)
VARIABLE last_time : time := time’left;
BEGIN
ASSERT (NOW - last_time = 20 ns)
REPORT “spike on clock”
SEVERITY WARNING;
last_time := now;
END PROCESS checktime;
END structural;


LÀM ƠN GIÚP EM VỚI GẦN NỘP BÀI RỒI, HUHU, em cám ơn lắm lắm.