Lỗi gán tín hiệu trong khối MUX(VHDL)

[tri2061990]

Code của em
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

----------------------------------------------
entity mux3 is
port(
Sel : in std_logic_vector(1 downto 0);
Din1 : in std_logic_vector(4 downto 0);
Din2 : in std_logic_vector(4 downto 0);
Din3 : in std_logic_vector(4 downto 0);
Dout : out std_logic_vector(4 downto 0)
);
end mux3;
-----------------------------------------------
architecture rtl of mux3 is
signal s1,s2,s3:std_logic_vector(4 downto 0);

begin
s1<=Din1;s2<=Din2;s3<=Din3;
with sel select
Dout<=s1 when "01",
Dout<=s2 when "00" ,
Dout<=s3 when "10",
Dout<=s2 when "11",
Unaffected when others;

end rtl;

Lỗi
# ** Error: mux3.vhd(24): Type error resolving infix expression "<=" as type ieee.std_logic_1164.std_logic_vector.
# ** Error: mux3.vhd(24): Cannot read output "dout".
# ** Error: mux3.vhd(25): Type error resolving infix expression "<=" as type ieee.std_logic_1164.std_logic_vector.
# ** Error: mux3.vhd(25): Cannot read output "dout".
# ** Error: mux3.vhd(26): Type error resolving infix expression "<=" as type ieee.std_logic_1164.std_logic_vector.
# ** Error: mux3.vhd(26): Cannot read output "dout".
# ** Error: mux3.vhd(29): VHDL Compiler exiting
# C:/Modeltech_6.3f/win32/vcom failed.

Bác nào giúp em với?

[Edimark]

Em bị sai lỗi cú pháp With signal Select trong VHDL, sửa lại như sau:

begin
s1<=Din1;s2<=Din2;s3<=Din3;
with sel select
Dout <= s1 when "01",
        s2 when "00",
        s3 when "10",
        s2 when "11",
        Unaffected when others;
end rtl;