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xin mấy cao thủ giúp mình xem đoạn code sau, ở đây mình không hiểu, ở đoạn lệnh gán tín hiệu: ALG_DATA <= ALG_DATA_INT;KS_CV<= CV_INT; nó thực hiện trước process main hay là sau?Nếu mà nó say ra trước thì mình không hiểu gán thế thì ALG_DATA ,KS_CV nhận 1 tín hiệu gì ở đây?Rất cảm ơn anh em!
library ieee;
use ieee.std_logic_1164.all;
use WORK.twofish_pack.all;
-- ================================================== =========================
-- =========================== Interface Description =========================
-- ================================================== =========================
entity INTERFACE is
port (clock : in std_logic;
reset : in std_logic;
DATA_LOAD : in std_logic; -- data load pulse
DATAIN : in SLV_128; -- 128 bit block
CV_LOAD : in std_logic; -- crypto variable load pulse
CVIN : in SLV_128;
ENC_DEC_B : in std_logic; -- '1' = encrypt, '0' = decrypt
CTRL_DATA_LOAD : out std_logic; -- data load signal to controller
CTRL_ENC_DEC_B : out std_logic;
ALG_DATA : out SLV_128; -- 128 bit data block to algorithm
KS_CVLOAD : out std_logic;
KS_CV : out SLV_128
);
end INTERFACE;
architecture INTERFACE_RTL of INTERFACE is
-- ================================================== =========================
-- =========================== Signal Definition =============================
-- ================================================== =========================
signal ALG_DATA_INT : SLV_128;
signal CV_INT : SLV_128;
begin
-- ================================================== =========================
-- =========================== Data Movement =================================
-- ================================================== =========================
ALG_DATA <= ALG_DATA_INT;
KS_CV <= CV_INT;
main: process( clock, reset )
begin
if reset = '1' then
CTRL_DATA_LOAD <= '0';
CTRL_ENC_DEC_B <= '0';
KS_CVLOAD <= '0';
CV_INT <= (others => '0');
ALG_DATA_INT <= (others => '0');
elsif clock'event and clock = '1' then
CTRL_DATA_LOAD <= DATA_LOAD; -- pass control signals through
CTRL_ENC_DEC_B <= ENC_DEC_B;
KS_CVLOAD <= CV_LOAD;
if DATA_LOAD = '1' then
ALG_DATA_INT <= DATAIN;
else
ALG_DATA_INT <= ALG_DATA_INT;
end if;
if CV_LOAD = '1' then -- latch CV
CV_INT <= CVIN;
else -- hold previous CV data
CV_INT <= CV_INT;
end if; -- CV_LOAD = '1'
end if; -- reset = '1'
end process;
end INTERFACE_RTL;
library ieee;
use ieee.std_logic_1164.all;
use WORK.twofish_pack.all;
-- ================================================== =========================
-- =========================== Interface Description =========================
-- ================================================== =========================
entity INTERFACE is
port (clock : in std_logic;
reset : in std_logic;
DATA_LOAD : in std_logic; -- data load pulse
DATAIN : in SLV_128; -- 128 bit block
CV_LOAD : in std_logic; -- crypto variable load pulse
CVIN : in SLV_128;
ENC_DEC_B : in std_logic; -- '1' = encrypt, '0' = decrypt
CTRL_DATA_LOAD : out std_logic; -- data load signal to controller
CTRL_ENC_DEC_B : out std_logic;
ALG_DATA : out SLV_128; -- 128 bit data block to algorithm
KS_CVLOAD : out std_logic;
KS_CV : out SLV_128
);
end INTERFACE;
architecture INTERFACE_RTL of INTERFACE is
-- ================================================== =========================
-- =========================== Signal Definition =============================
-- ================================================== =========================
signal ALG_DATA_INT : SLV_128;
signal CV_INT : SLV_128;
begin
-- ================================================== =========================
-- =========================== Data Movement =================================
-- ================================================== =========================
ALG_DATA <= ALG_DATA_INT;
KS_CV <= CV_INT;
main: process( clock, reset )
begin
if reset = '1' then
CTRL_DATA_LOAD <= '0';
CTRL_ENC_DEC_B <= '0';
KS_CVLOAD <= '0';
CV_INT <= (others => '0');
ALG_DATA_INT <= (others => '0');
elsif clock'event and clock = '1' then
CTRL_DATA_LOAD <= DATA_LOAD; -- pass control signals through
CTRL_ENC_DEC_B <= ENC_DEC_B;
KS_CVLOAD <= CV_LOAD;
if DATA_LOAD = '1' then
ALG_DATA_INT <= DATAIN;
else
ALG_DATA_INT <= ALG_DATA_INT;
end if;
if CV_LOAD = '1' then -- latch CV
CV_INT <= CVIN;
else -- hold previous CV data
CV_INT <= CV_INT;
end if; -- CV_LOAD = '1'
end if; -- reset = '1'
end process;
end INTERFACE_RTL;
.
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