nghe thầy bảo sau này mấy cty kiểu gì cũng có cái nài 
ai có bộ cài hoặc có ***** thì cho mình với mình chỉ cần 1 trong 2 thôi
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module counter (/*AUTOARG*/
// Outputs
mm_o, ss_o, hh_o,
// Inputs
clk, rst_n, set_h, set_m, set_s
) ;
// Parameter
parameter
INIT = 3'b000,
START = 3'b001,
SET_H = 3'b011,
SET_M = 3'b111,
SET_S = 3'b110;
parameter
S_WIDTH = 3,
CNT_WIDTH = 6;
// Inputs
input clk, rst_n;
input set_h, set_m, set_s;
// Outputs
output [CNT_WIDTH-1:0] mm_o, ss_o;
output [4:0] hh_o;
// Regs and Signals
reg [CNT_WIDTH-1:0] m_o, s_o;
reg [4:0] h_o;
reg [S_WIDTH-1:0] state, next_state;
always @(posedge clk, negedge rst_n)
begin
if(rst_n == 1'b0)
state <= INIT;
else
state <= next_state;
end
always @(posedge clk)
begin
case(state)
INIT:
begin
next_state = START;
end
START:
begin
if(set_h == 1'b1)
next_state = SET_H;
else if(set_m == 1'b1)
next_state = SET_M;
else if(set_s == 1'b1)
next_state = SET_S;
else
next_state = START;
end // case: START
SET_H:
begin
if(set_h == 1'b1)
next_state = SET_H;
else if(set_m == 1'b1)
next_state = SET_M;
else if(set_s == 1'b1)
next_state = SET_S;
else
next_state = START;
end
SET_M:
begin
if(set_h == 1'b1)
next_state = SET_H;
else if(set_m == 1'b1)
next_state = SET_M;
else if(set_s == 1'b1)
next_state = SET_S;
else
next_state = START;
end
SET_S:
begin
if(set_h == 1'b1)
next_state = SET_H;
else if(set_m == 1'b1)
next_state = SET_M;
else if(set_s == 1'b1)
next_state = SET_S;
else
next_state = START;
end
default:
next_state = INIT;
endcase // case (state)
end // always @ (*)
always @(posedge clk, negedge rst_n)
begin
if(rst_n == 1'b0)
begin
h_o = 0;
m_o = 0;
s_o = 0;
end
else
begin
case(state)
INIT:
begin
h_o = 0;
m_o = 0;
s_o = 0;
end
START:
begin
s_o = s_o + 1;
if(s_o == 6'd59)
begin
s_o = 0;
m_o = m_o + 1;
if(m_o == 6'd59)
begin
m_o = 0;
h_o = h_o + 1;
if(h_o == 5'd23)
h_o = 0;
end
end // if (s_o == 6'd59)
end // case: START
SET_H:
begin
if(h_o == 5'd23)
h_o = 0;
else
h_o = h_o + 1;
end
SET_M:
begin
if(m_o == 6'd59)
m_o = 0;
else
m_o = m_o + 1;
end
SET_S:
begin
if(s_o == 6'd59)
s_o = 0;
else
s_o = s_o + 1;
end
default:
begin
h_o = h_o;
m_o = m_o;
s_o = s_o;
end
endcase // case (state)
end // else: !if(rst_n == 1'b0)
end // always @ (posedge clk, negedge rst_n)
assign hh_o = h_o;
assign mm_o = m_o;
assign ss_o = s_o;
endmodule // counter
module counter (/*AUTOARG*/
// Outputs
mm_o, ss_o, hh_o,
// Inputs
clk, rst_n, set_h, set_m, set_s
) ;
// Parameter
parameter
INIT = 3'b000,
START = 3'b001,
SET_H = 3'b011,
SET_M = 3'b111,
SET_S = 3'b110;
parameter
S_WIDTH = 3,
CNT_WIDTH = 6;
// Inputs
input clk, rst_n;
input set_h, set_m, set_s;
// Outputs
output [CNT_WIDTH-1:0] mm_o, ss_o;
output [4:0] hh_o;
// Regs and Signals
reg [CNT_WIDTH-1:0] m_o, s_o;
reg [4:0] h_o;
reg [S_WIDTH-1:0] state, next_state;
always @(posedge clk, negedge rst_n)
begin
if(rst_n == 1'b0)
state <= INIT;
else
state <= next_state;
end
always @(posedge clk)
begin
case(state)
INIT:
begin
next_state = START;
end
START:
begin
if(set_h == 1'b1)
next_state = SET_H;
else if(set_m == 1'b1)
next_state = SET_M;
else if(set_s == 1'b1)
next_state = SET_S;
else
next_state = START;
end // case: START
SET_H:
begin
if(set_h == 1'b1)
next_state = SET_H;
else if(set_m == 1'b1)
next_state = SET_M;
else if(set_s == 1'b1)
next_state = SET_S;
else
next_state = START;
end
SET_M:
begin
if(set_h == 1'b1)
next_state = SET_H;
else if(set_m == 1'b1)
next_state = SET_M;
else if(set_s == 1'b1)
next_state = SET_S;
else
next_state = START;
end
SET_S:
begin
if(set_h == 1'b1)
next_state = SET_H;
else if(set_m == 1'b1)
next_state = SET_M;
else if(set_s == 1'b1)
next_state = SET_S;
else
next_state = START;
end
default:
next_state = INIT;
endcase // case (state)
end // always @ (*)
always @(posedge clk, negedge rst_n)
begin
if(rst_n == 1'b0)
begin
h_o = 0;
m_o = 0;
s_o = 0;
end
else
begin
case(state)
INIT:
begin
h_o = 0;
m_o = 0;
s_o = 0;
end
START:
begin
s_o = s_o + 1;
if(s_o == 6'd59)
begin
s_o = 0;
m_o = m_o + 1;
if(m_o == 6'd59)
begin
m_o = 0;
h_o = h_o + 1;
if(h_o == 5'd23)
h_o = 0;
end
end // if (s_o == 6'd59)
end // case: START
SET_H:
begin
if(h_o == 5'd23)
h_o = 0;
else
h_o = h_o + 1;
end
SET_M:
begin
if(m_o == 6'd59)
m_o = 0;
else
m_o = m_o + 1;
end
SET_S:
begin
if(s_o == 6'd59)
s_o = 0;
else
s_o = s_o + 1;
end
default:
begin
h_o = h_o;
m_o = m_o;
s_o = s_o;
end
endcase // case (state)
end // else: !if(rst_n == 1'b0)
end // always @ (posedge clk, negedge rst_n)
assign hh_o = h_o;
assign mm_o = m_o;
assign ss_o = s_o;
endmodule // counter
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