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Code:
module chia(A, B, Q, S, Y);
input [15:0] A;
input [7:0] B;
output [7:0] Q, S, Y;
reg [7:0] Q, S, Y, D;
reg [15:0] temps, temp, not_B, temp1;
integer j;
always @ ( A or B)
begin
begin
D = ~B;
temp = B<<8;
not_B = D <<8;
temps = A <<1;
end
for (j = 7 ; j >= 0; j = j- 1)
begin
begin
temp1 = temps <<1;
Y = temp1 > temp;
end
if ( Y==1)
begin
Q[j] = 1'b1;
temps = temps + not_B;
end
else
begin
Q[j] = 1'b0;
temps = temps <<1;
end
S[7:0] = temps>>8;
end
end
endmodule
Code:
Info: Running Quartus II Analysis & Synthesis Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition Info: Processing started: Thu Dec 03 13:05:06 2009 Info: Command: quartus_map --read_settings_files=on --write_settings_files=off chia -c chia Info: Found 1 design units, including 1 entities, in source file chia.v Info: Found entity 1: chia Info: Elaborating entity "chia" for the top level hierarchy Warning (10230): Verilog HDL assignment warning at chia.v(34): truncated value with size 16 to match size of target (8) Warning: Output pins are stuck at VCC or GND Warning (13410): Pin "Y[1]" is stuck at GND Warning (13410): Pin "Y[2]" is stuck at GND Warning (13410): Pin "Y[3]" is stuck at GND Warning (13410): Pin "Y[4]" is stuck at GND Warning (13410): Pin "Y[5]" is stuck at GND Warning (13410): Pin "Y[6]" is stuck at GND Warning (13410): Pin "Y[7]" is stuck at GND Warning: Design contains 1 input pin(s) that do not drive logic Warning (15610): No output dependent on input pin "A[15]" Info: Implemented 306 device resources after synthesis - the final resource count might be different Info: Implemented 24 input pins Info: Implemented 24 output pins Info: Implemented 258 logic cells Info: Quartus II Analysis & Synthesis was successful. 0 errors, 11 warnings Info: Peak virtual memory: 176 megabytes Info: Processing ended: Thu Dec 03 13:05:10 2009 Info: Elapsed time: 00:00:04 Info: Total CPU time (on all processors): 00:00:05 Info: ******************************************************************* Info: Running Quartus II Fitter Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition Info: Processing started: Thu Dec 03 13:05:12 2009 Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off chia -c chia Info: Selected device EP2C5F256C8 for design "chia" Info: Low junction temperature is 0 degrees C Info: High junction temperature is 85 degrees C Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time Warning: Feature LogicLock is not available with your current license Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices Info: Device EP2C5F256I8 is compatible Info: Device EP2C5AF256I8 is compatible Info: Device EP2C8F256C8 is compatible Info: Device EP2C8F256I8 is compatible Info: Device EP2C8AF256I8 is compatible Info: Fitter converted 3 user pins into dedicated programming pins Info: Pin ~ASDO~ is reserved at location C3 Info: Pin ~nCSO~ is reserved at location F4 Info: Pin ~LVDS41p/nCEO~ is reserved at location N14 Warning: No exact pin location assignment(s) for 48 pins of 48 total pins Info: Pin A[15] not assigned to an exact location on the device Info: Pin Q[0] not assigned to an exact location on the device Info: Pin Q[1] not assigned to an exact location on the device Info: Pin Q[2] not assigned to an exact location on the device Info: Pin Q[3] not assigned to an exact location on the device Info: Pin Q[4] not assigned to an exact location on the device Info: Pin Q[5] not assigned to an exact location on the device Info: Pin Q[6] not assigned to an exact location on the device Info: Pin Q[7] not assigned to an exact location on the device Info: Pin S[0] not assigned to an exact location on the device Info: Pin S[1] not assigned to an exact location on the device Info: Pin S[2] not assigned to an exact location on the device Info: Pin S[3] not assigned to an exact location on the device Info: Pin S[4] not assigned to an exact location on the device Info: Pin S[5] not assigned to an exact location on the device Info: Pin S[6] not assigned to an exact location on the device Info: Pin S[7] not assigned to an exact location on the device Info: Pin Y[0] not assigned to an exact location on the device Info: Pin Y[1] not assigned to an exact location on the device Info: Pin Y[2] not assigned to an exact location on the device Info: Pin Y[3] not assigned to an exact location on the device Info: Pin Y[4] not assigned to an exact location on the device Info: Pin Y[5] not assigned to an exact location on the device Info: Pin Y[6] not assigned to an exact location on the device Info: Pin Y[7] not assigned to an exact location on the device Info: Pin B[7] not assigned to an exact location on the device Info: Pin B[6] not assigned to an exact location on the device Info: Pin A[13] not assigned to an exact location on the device Info: Pin B[5] not assigned to an exact location on the device Info: Pin A[12] not assigned to an exact location on the device Info: Pin B[4] not assigned to an exact location on the device Info: Pin A[11] not assigned to an exact location on the device Info: Pin B[3] not assigned to an exact location on the device Info: Pin A[10] not assigned to an exact location on the device Info: Pin B[2] not assigned to an exact location on the device Info: Pin A[9] not assigned to an exact location on the device Info: Pin B[1] not assigned to an exact location on the device Info: Pin A[8] not assigned to an exact location on the device Info: Pin B[0] not assigned to an exact location on the device Info: Pin A[7] not assigned to an exact location on the device Info: Pin A[6] not assigned to an exact location on the device Info: Pin A[5] not assigned to an exact location on the device Info: Pin A[3] not assigned to an exact location on the device Info: Pin A[4] not assigned to an exact location on the device Info: Pin A[2] not assigned to an exact location on the device Info: Pin A[1] not assigned to an exact location on the device Info: Pin A[0] not assigned to an exact location on the device Info: Pin A[14] not assigned to an exact location on the device Info: Fitter is using the Classic Timing Analyzer Info: Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time. Info: Starting register packing Info: Finished register packing Extra Info: No registers were packed into other blocks Info: Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement Info: Number of I/O pins in group: 48 (unused VREF, 3.3V VCCIO, 24 input, 24 output, 0 bidirectional) Info: I/O standards used: 3.3-V LVTTL. Info: I/O bank details before I/O pin placement Info: Statistics of I/O banks Info: I/O bank number 1 does not use VREF pins and has undetermined VCCIO pins. 2 total pin(s) used -- 33 pins available Info: I/O bank number 2 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 43 pins available Info: I/O bank number 3 does not use VREF pins and has undetermined VCCIO pins. 1 total pin(s) used -- 38 pins available Info: I/O bank number 4 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 41 pins available Info: Fitter preparation operations ending: elapsed time is 00:00:01 Info: Fitter placement preparation operations beginning Info: Fitter placement preparation operations ending: elapsed time is 00:00:00 Info: Fitter placement operations beginning Info: Fitter placement was successful Info: Fitter placement operations ending: elapsed time is 00:00:00 Info: Fitter routing operations beginning Info: Average interconnect usage is 1% of the available device resources Info: Peak interconnect usage is 2% of the available device resources in the region that extends from location X14_Y0 to location X28_Y14 Info: Fitter routing operations ending: elapsed time is 00:00:00 Info: The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time. Info: Optimizations that may affect the design's routability were skipped Info: Optimizations that may affect the design's timing were skipped Info: Started post-fitting delay annotation Warning: Found 24 output pins without output pin load capacitance assignment Info: Pin "Q[0]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis Info: Pin "Q[1]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis Info: Pin "Q[2]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis Info: Pin "Q[3]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis Info: Pin "Q[4]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis Info: Pin "Q[5]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis Info: Pin "Q[6]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis Info: Pin "Q[7]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis Info: Pin "S[0]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis Info: Pin "S[1]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis Info: Pin "S[2]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis Info: Pin "S[3]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis Info: Pin "S[4]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis Info: Pin "S[5]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis Info: Pin "S[6]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis Info: Pin "S[7]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis Info: Pin "Y[0]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis Info: Pin "Y[1]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis Info: Pin "Y[2]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis Info: Pin "Y[3]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis Info: Pin "Y[4]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis Info: Pin "Y[5]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis Info: Pin "Y[6]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis Info: Pin "Y[7]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis Info: Delay annotation completed successfully Warning: Following 7 pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results Info: Pin Y[1] has GND driving its datain port Info: Pin Y[2] has GND driving its datain port Info: Pin Y[3] has GND driving its datain port Info: Pin Y[4] has GND driving its datain port Info: Pin Y[5] has GND driving its datain port Info: Pin Y[6] has GND driving its datain port Info: Pin Y[7] has GND driving its datain port Warning: The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'. Info: Quartus II Fitter was successful. 0 errors, 5 warnings Info: Peak virtual memory: 198 megabytes Info: Processing ended: Thu Dec 03 13:05:16 2009 Info: Elapsed time: 00:00:04 Info: Total CPU time (on all processors): 00:00:03
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