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The billion-transistor era of application specific semiconductor chips will technologically be entered within less than five years. The design of such chips for various applications, like telecommunications, faces demanding challenges due to huge complexity of systems and increasing design productivity gap. To meet this challenge, a chip development platform and design methodology is required which allows reuse at all levels of design.
In this project, we develop a new architecture template, called Network on chip (NOC), for future integrated telecommunication systems. NoC template provides vertical integration of physical and architectural levels in system design. In the NoC template, a chip consists of contigous areas called regions, which are physically isolated from each other but have special mechanism for communication among each other. A region of NoC will be composed of computing resources in the form of processor cores and field programmable logic blocks, distributed storage resources, programmable I/O and all these resources interconnected by a switching fabric, allowing any resource to communicate with any other resource.
This project is an EXSITE project, funded by TEKES, VINNOVA, NOKIA and Ericsson.
It is jointly conducted by the Laboratory of Electronics and Computer Systems at the Royal Institute of Technology and VTT. It commenced on January 1, 2001, and is due to end on December 31, 2003.
The billion-transistor era of application specific semiconductor chips will technologically be entered within less than five years. The design of such chips for various applications, like telecommunications, faces demanding challenges due to huge complexity of systems and increasing design productivity gap. To meet this challenge, a chip development platform and design methodology is required which allows reuse at all levels of design.
In this project, we develop a new architecture template, called Network on chip (NOC), for future integrated telecommunication systems. NoC template provides vertical integration of physical and architectural levels in system design. In the NoC template, a chip consists of contigous areas called regions, which are physically isolated from each other but have special mechanism for communication among each other. A region of NoC will be composed of computing resources in the form of processor cores and field programmable logic blocks, distributed storage resources, programmable I/O and all these resources interconnected by a switching fabric, allowing any resource to communicate with any other resource.
This project is an EXSITE project, funded by TEKES, VINNOVA, NOKIA and Ericsson.
It is jointly conducted by the Laboratory of Electronics and Computer Systems at the Royal Institute of Technology and VTT. It commenced on January 1, 2001, and is due to end on December 31, 2003.
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