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void FEI_TO_PEE()
{
FEI_FBE();
FBE_PBE();
PBE_PEE();
}
static const uint8_t MCGTransitionMatrix[8][8] = {
/* This matrix defines which mode is next in the MCG Mode state diagram in transitioning from the
current mode to a target mode
FEI FBI BLPI BLPE FEE FBE PBE PEE
0 1 2 3 4 5 6 7
*/
{ MCG_MODE_FEI, MCG_MODE_FBI, MCG_MODE_FBI, MCG_MODE_FBE, MCG_MODE_FEE, MCG_MODE_FBE, MCG_MODE_FBE, MCG_MODE_FBE}, /* FEI */
{ MCG_MODE_FEI, MCG_MODE_FBI, MCG_MODE_BLPI, MCG_MODE_FBE, MCG_MODE_FEE, MCG_MODE_FBE, MCG_MODE_FBE, MCG_MODE_FBE},/* FBI */
{ MCG_MODE_FBI, MCG_MODE_FBI, MCG_MODE_BLPI, MCG_MODE_FBI, MCG_MODE_FBI, MCG_MODE_FBI, MCG_MODE_FBI, MCG_MODE_FBI},/* BLPI */
{ MCG_MODE_FBE, MCG_MODE_FBE, MCG_MODE_FBE, MCG_MODE_BLPE, MCG_MODE_FBE, MCG_MODE_FBE, MCG_MODE_PBE, MCG_MODE_PBE},/* BLPE */
{ MCG_MODE_FEI, MCG_MODE_FBI, MCG_MODE_FBI, MCG_MODE_FBE, MCG_MODE_FEE, MCG_MODE_FBE, MCG_MODE_FBE, MCG_MODE_FBE},/* FEE */
{ MCG_MODE_FEI, MCG_MODE_FBI, MCG_MODE_FBI, MCG_MODE_BLPE, MCG_MODE_FEE, MCG_MODE_FBE, MCG_MODE_PBE, MCG_MODE_PBE},/* FBE */
{ MCG_MODE_FBE, MCG_MODE_FBE, MCG_MODE_FBE, MCG_MODE_BLPE, MCG_MODE_FBE, MCG_MODE_FBE, MCG_MODE_PBE, MCG_MODE_PEE},/* PBE */
{ MCG_MODE_PBE, MCG_MODE_PBE, MCG_MODE_PBE, MCG_MODE_PBE, MCG_MODE_PBE, MCG_MODE_PBE, MCG_MODE_PBE, MCG_MODE_PEE} /* PEE */
};
static void Cpu_SetMCG(uint8_t TargetMCGMode)
{
uint8_t NextMCGMode;
NextMCGMode = Cpu_GetCurrentMCGMode(); /* Identify the currently active MCG mode */
do {
NextMCGMode = MCGTransitionMatrix[NextMCGMode][TargetMCGMode]; /* Get the next MCG mode on the path to the target MCG mode */
switch (NextMCGMode) { /* Set the next MCG mode on the path to the target MCG mode */
case MCG_MODE_FEI:
MCG_FEI();
break;
case MCG_MODE_FBI:
MCG_FBI();
break;
case MCG_MODE_BLPI:
MCG_BLPI();
break;
case MCG_MODE_BLPE:
MCG_BLPE();
break;
case MCG_MODE_FBE:
MCG_FBE();
break;
case MCG_MODE_FEE:
MCG_FEE();
break;
case MCG_MODE_PBE:
MCG_PBE();
break;
case MCG_MODE_PEE:
MCG_PEE();
break;
default:
break;
}
} while (TargetMCGMode != NextMCGMode); /* Loop until the target MCG mode is set */
}
uint8_t Cpu_GetCurrentMCGMode(void)
{
switch (MCG->C1 & MCG_C1_CLKS_MASK)
{
case MCG_C1_CLKS(0): // PLL / FLL External
if(MCG->C6 & MCG_C6_PLLS_MASK)
return MCG_MODE_PEE;
else
{
if(MCG->C1 & MCG_C1_IREFS_MASK)
return MCG_MODE_FEI;
else
return MCG_MODE_FEE;
}
case MCG_C1_CLKS(1): // Internal Clock
if ((MCG->C2 & MCG_C2_LP_MASK) == MCG_C2_LP_MASK)
{
/* Low power mode is enabled */
return MCG_MODE_BLPI;
}
else
{
/* Low power mode is disabled */
return MCG_MODE_FBI;
}
case MCG_C1_CLKS(2): // External Clock
if ((MCG->C2 & MCG_C2_LP_MASK) == MCG_C2_LP_MASK)
{
/* Low power mode is enabled */
return MCG_MODE_BLPE;
}
else
{
if ((MCG->C6 & MCG_C6_PLLS_MASK) == MCG_C6_PLLS_MASK)
{
/* PLL is selected */
return MCG_MODE_PBE;
}
else
{
/* FLL is selected */
return MCG_MODE_FBE;
}
}
default:
return 0x00U;
}
}
// switch to FEE 20MHz FLL
void MCG_FEE(void)
{
MCG->C2 |= MCG_C2_RANGE0(3) |// Very high frequency range selected for the crystal oscillator
MCG_C2_EREFS0_MASK |
MCG_C2_HGO0_MASK ;
MCG->C1 &= ~MCG_C1_FRDIV_MASK;
MCG->C1 |= MCG_C1_FRDIV(3); // Divide Factor is 256. 8000 / 256 = 31.25kHz
MCG->C1 &= ~MCG_C1_IREFS_MASK; // External clock (8MHz) for FLL
MCG->C4 &= ~MCG_C4_DRST_DRS_MASK;
MCG->C4 &= ~MCG_C4_DMX32_MASK;// 31.25 * 640 = 20000kHz
MCG->C6 &= ~MCG_C6_PLLS_MASK;// select FLL
MCG->C1 &= ~MCG_C1_CLKS_MASK; // Output of FLL is selected for MCGOUTCLK
while((MCG->S & MCG_S_OSCINIT0_MASK) == 0); // wait for osc init
while((MCG->S & MCG_S_PLLST_MASK) != 0); // wait for FLL
while((MCG->S & MCG_S_IREFST_MASK) != 0); // wait for External clock is selected
while((MCG->S & MCG_S_CLKST_MASK) != 0); // wait for FLL is selected
}
// switch to FBI 4MHz Internal clock
void MCG_FBI(void)
{
MCG->SC &= ~MCG_SC_FCRDIV_MASK; // Divide Factor is 1
MCG->C1 &= ~MCG_C1_CLKS_MASK;
MCG->C1 |= MCG_C1_IREFS_MASK |// Enable MCGIRCLK for uart0
MCG_C1_IRCLKEN_MASK;
MCG->C2 &= ~MCG_C2_LP_MASK; // FLL or PLL is not disabled in bypass modes
MCG->C2 |= MCG_C2_IRCS_MASK; // Fast internal reference clock selected
MCG->C6 &= ~MCG_C6_PLLS_MASK;
MCG->C1 |= MCG_C1_CLKS(1); // Internal reference clock is selected
while((MCG->S & MCG_S_IRCST_MASK) == 0);
while((MCG->S & MCG_S_CLKST_MASK) != MCG_S_CLKST(1)); // wait for Internal clock is selected
}
// switch to FBE 8MHz External crystal
void MCG_FBE(void)
{
MCG->C6 &= ~MCG_C6_CME0_MASK;
MCG->C2 |= MCG_C2_RANGE0(3) |// Very high frequency range selected for the crystal oscillator
MCG_C2_EREFS0_MASK |
MCG_C2_HGO0_MASK ;
MCG->C4 &= ~MCG_C4_DRST_DRS_MASK;
MCG->C4 &= ~MCG_C4_DMX32_MASK;
MCG->C4 |= MCG_C4_DRST_DRS(1);// 32.768 * 1280 = 41943.04kHz
MCG->C6 &= ~MCG_C6_PLLS_MASK;// select FLL
MCG->C1 &= ~MCG_C1_CLKS_MASK;
MCG->C1 |= MCG_C1_CLKS(2); // Output of FLL is selected for MCGOUTCLK
while((MCG->S & MCG_S_OSCINIT0_MASK) == 0); // wait for osc init
while((MCG->S & MCG_S_PLLST_MASK) != 0); // wait for FLL
while((MCG->S & MCG_S_CLKST_MASK) != MCG_S_CLKST(2)); // wait for EXTAL is selected
}
// switch to PBE 8MHz External crystal
void MCG_PBE(void)
{
MCG->C6 &= ~MCG_C6_CME0_MASK;
MCG->C2 &= ~MCG_C2_LP_MASK;
MCG->C2 |= MCG_C2_RANGE0(3) |// Very high frequency range selected for the crystal oscillator
MCG_C2_EREFS0_MASK |
MCG_C2_HGO0_MASK ;
MCG->C5 &= ~MCG_C5_PRDIV0_MASK;
MCG->C5 |= MCG_C5_PRDIV0(4 - 1); // External clock div 4
MCG->C6 &= ~MCG_C6_VDIV0_MASK;
MCG->C6 |= MCG_C6_VDIV0(24 - 24) | // Mul 24. 8 / 4 * 24 = 48MHz
MCG_C6_CME0_MASK |
MCG_C6_PLLS_MASK;
MCG->C1 &= ~MCG_C1_CLKS_MASK;
MCG->C1 |= MCG_C1_CLKS(2); // Output of ExTAL is selected for MCGOUTCLK
while((MCG->S & MCG_S_OSCINIT0_MASK) == 0); // wait for osc init.
while((MCG->S & MCG_S_PLLST_MASK) != MCG_S_PLLST_MASK); // wait for PLL
while((MCG->S & MCG_S_CLKST_MASK) != MCG_S_CLKST(2)); // wait for EXTAL is selected
}
// switch to PEE 48MHz PLL
void MCG_PEE(void)
{
MCG->C6 &= ~MCG_C6_CME0_MASK;
MCG->C2 &= ~MCG_C2_LP_MASK;
MCG->C2 |= MCG_C2_RANGE0(3) |// Very high frequency range selected for the crystal oscillator
MCG_C2_EREFS0_MASK |
MCG_C2_HGO0_MASK ;
MCG->C5 &= ~MCG_C5_PRDIV0_MASK;
MCG->C5 |= MCG_C5_PRDIV0(4 - 1); // External clock div 4
MCG->C6 &= ~MCG_C6_VDIV0_MASK;
MCG->C6 |= MCG_C6_VDIV0(24 - 24) | // Mul 24. 8 / 4 * 24 = 48MHz
MCG_C6_CME0_MASK |
MCG_C6_PLLS_MASK;
MCG->C1 &= ~MCG_C1_CLKS_MASK; // Output of PLL is selected for MCGOUTCLK
while((MCG->S & MCG_S_OSCINIT0_MASK) == 0); // wait for osc init.
while((MCG->S & MCG_S_PLLST_MASK) != MCG_S_PLLST_MASK); // wait for PLL
while((MCG->S & MCG_S_CLKST_MASK) != MCG_S_CLKST(3)); // wait for PLL is selected
}
// switch to BLPI MCGOUTCLK = 4MHz Internal clock
void MCG_BLPI(void)
{
MCG->C6 &= ~MCG_C6_CME0_MASK;
MCG->C2 |= MCG_C2_IRCS_MASK; // select slow IRC
MCG->C1 &= ~MCG_C1_CLKS_MASK;
MCG->C1 |= MCG_C1_CLKS(1);
MCG->C2 |= MCG_C2_LP_MASK; // disable FLL/PLL in low power mode
while((MCG->S & MCG_S_IRCST_MASK) == 0);
while((MCG->S & MCG_S_CLKST_MASK) != MCG_S_CLKST(1)); // wait for Internal clock is selected
}
// switch to BLPE MCGOUTCLK = 8MHz External clock
void MCG_BLPE(void)
{
MCG->C6 &= ~MCG_C6_CME0_MASK;
MCG->C1 &= ~MCG_C1_CLKS_MASK;
MCG->C2 |= MCG_C2_RANGE0(3) |// Very high frequency range selected for the crystal oscillator
MCG_C2_EREFS0_MASK |
MCG_C2_HGO0_MASK ;
MCG->C1 |= MCG_C1_CLKS(2);
MCG->C2 |= MCG_C2_LP_MASK; // disable FLL/PLL in low power mode
MCG->C6 |= MCG_C6_CME0_MASK; // enable CMEO
while((MCG->S & MCG_S_OSCINIT0_MASK) == 0); // wait for osc init.
while((MCG->S & MCG_S_CLKST_MASK) != MCG_S_CLKST(2)); // wait for EXTAL is selected
}
SIM->CLKDIV1 = SIM_CLKDIV1_OUTDIV1(0) | // core/system clock = 48 / 1 = 48MHz
SIM_CLKDIV1_OUTDIV4(1); // flash/bus clock = 48 / 2 = 24MHz
có thể viết như sau để dễ tính toán khi xem lại code
SIM->CLKDIV1 = SIM_CLKDIV1_OUTDIV1(1 - 1) | // core/system clock = 48 / 1 = 48MHz
SIM_CLKDIV1_OUTDIV4(2 - 1); // flash/bus clock = 48 / 2 = 24MHz
SIM->SOPT2 |= SIM_SOPT2_UART0SRC(3);
SIM->SCGC5 |= SIM_SCGC5_PORTA_MASK Set bit 9 của thanh ghi SIM_SCGC5 lên 1
SIM->SCGC5 &= ~SIM_SCGC5_PORTA_MASK Clear bit 9 của thanh ghi SIM_SCGC5 về 0
Em đã chuyển sang chế độ "Open SDA Application" nhưng vẫn bị cái lỗi đó anh ah
Em đã chuyển sang chế độ "Open SDA Application" nhưng vẫn bị cái lỗi đó anh ahvoid gpio_init(PORT_Type * port_address, GPIO_Type * gpio_address, uint32_t pin)
{
port_address->PCR[pin] |= PORT_PCR_MUX(1);// Alternative 1 (GPIO)
gpio_address->PSOR = GPIO_PSOR_PTSO(1<<pin);// Set PIN 1 logic 1
gpio_address->PDDR = GPIO_PDDR_PDD(1<<pin);// set pin output
}
void gpio_pin_toggle(GPIO_Type * gpio_address, uint32_t pin)
{
if(pin > 32)
gpio_address->PTOR |= GPIO_PSOR_PTSO_MASK;// toggle all pin
else
gpio_address->PTOR |= GPIO_PSOR_PTSO(1 << pin);// toggle specified pin
}
void gpio_pin_set(GPIO_Type * gpio_address, uint32_t pin)
{
if(pin > 32)
gpio_address->PSOR |= GPIO_PSOR_PTSO_MASK;// set all pin
else
gpio_address->PSOR |= GPIO_PSOR_PTSO(1 << pin);// set specified pin
}
void gpio_pin_clear(GPIO_Type * gpio_address, uint32_t pin)
{
if(pin > 32)
gpio_address->PCOR |= GPIO_PSOR_PTSO_MASK;// clear all pin
else
gpio_address->PCOR |= GPIO_PCOR_PTCO(1 << pin);// clear specified pin
}
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